STARC TOP   about STARC Joint Research SoC Design Technology SoC Design Technology Design Methodology IP Reuse System-Level Design Test Methodology Physical Design Low Power Technology SoC Platform Events Downloads     SoC Design Technology Development Japanese Goals To develop new design methods and design technologies that will dramatically improve SoC (System on a Chip) design productivity and will enable the most effective use of advanced semiconductor technologies, as well as to promote the standardization of these methods and technologies 　System-Level Design Automation Technologies Development of design methods and design automation technologies, including system-level, architecture, and software, required to optimize design and reduce the time required for Soc design, which continues to increase in scale 　IP Reuse and Sharing Technologies Establishment of design methods for promoting the reuse of design assets (Intellecctual Property) relating to SoC design, and establishment of technical foundations for promoting the sharing of such Intellecctual Property 　Circuit/Layout Design Optimization Technologies Development of circuit/layout design optimization technologies and high-accuracy simulation/modeling technologies for ultra-miniaturization of CMOS 　Low Power Technology of SoC Development of low power technology of CPU and analog IP from architecture and circuit levels 　Previous　Project VCDS Project（2000/4-2003/3) Terms of use Privacy Policy Copyright(C) 1996-2005 STARC All Rights Reserved.