| Development of LSI Design Technologies |
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Japanese
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- STARC has cooperated with client companies to reinvent and improve design methodologies in order to empower designers to easily migrate to the shrinking technology nodes. At present, STARC is working on design methodologies for the upcoming 32-nm process. Additionally, STARC is now involved in the development of unique circuit technologies that will lend themselves well to the advanced technology nodes.
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- A number of issues have come to light within the area of ultra-miniature technologies under 65nm, including the design dependency of processing accuracy in semiconductor construction and production fluctuations. It is for this reason that DFM (Design for Manufacturing) has become extremely important. STARC develops and promotes the practical application of DFM technologies with the aim of achieving 45nm, 35nm SoC.
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- With the shrinking process geometries, chip designers and architects must now address new types of faults such as bridging and small-delay faults in addition to traditionally covered stuck-at and transition faults. The emergence of deep nanometer designs introduces new challenges in terms of test time and so on. To address this problem, STARC is promoting the development and deployment of the techniques that make it possible to perform testing and fault diagnosis on 45nm and 32nm SoCs in a realistic time; test techniques that address process variations; highly accurate test and fault diagnosis methods and so on. Additionally, STARC will create a standardized test environment in which all necessary tests can be performed and which allows easy interfacing to a wide range of tools from ATE and EDA vendors.
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- As analog IP cores become increasingly sophisticated and supply voltages continue to drop, the increased complexity of mixed-signal design poses additional challenges to the design community. With device scaling, in-die performance variations among transistors and other elements increase, 3D parasitic extraction becomes more complicated due to complex circuit structures, and the physical effects emerge as key design considerations with serious implications. Thus, reducing design cycles is the biggest concern to be addressed. STARC is committed to the development of analog and mixed-signal design flows that will eliminate the need for iterations, so designers will be able to get their prototypes right the first time. Its main focuses are design planning with constraints and tight interactions between circuit design and layout, which are jointly being investigated by the participating clients, EDA vendors and academia.
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- STARC aims to serve as a bridge between academic research and industrial applications. For the 65-nm node and below, STARC is using its shuttle services to fabricate prototype chips for innovative circuit architectures solicited from universities in order to help facilitate practical use of their research results. For the industry to survive the global competition, it is essential to build deeper cooperation with universities to leverage their expertise more than ever before. Circuit architecture development is one of the principal schemes to promote industry-academic collaboration. This program is also highly valued at universities as a means of spurring research, offering advanced education and developing excellent human resources.
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- While immediate actions are necessary to combat global warming, the power consumption of many information appliances is expected to increase dramatically. Manufacturers are being required to further reduce the power consumed by all kinds of electronic products, including computer servers, information terminals and home appliances. Green IT consists of two actions: “Green of IT” (development of less energy-hungry products) and “Green by IT” (their applications for energy saving). In line with this objective, STARC is working on logic, memory, analog, power supply, wireless circuit and system technologies to slash the power consumption of SoC chips to 1/10th of the current levels. To reduce dynamic power, reducing the supply voltage may be the first choice, but at an ultra-low voltage of 0.5 V or less, variability becomes a critical issue. To overcome this challenge, STARC is promoting joint cooperation between industry and academia.
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- STARC has been working on standardization of design data and methodologies to help improve design productivity and quality, thereby reducing design costs.
STARC has created the following design guides as standard reference materials to spread consistent design practices among the design community: the RTL Design Style Guide that describes good coding practices; the Transaction-Level Modeling (TLM) Guide that helps facilitate use of TLM-based design; the IP Functional Verification Guide intended to help improve the quality of functional verification; and the STIL (Standard Test Interface Language) Usage Guide that discusses how to construct an SoC test environment.
STARC is now putting efforts to standardize and proliferate HiSIM, a surface-potential-based physical transistor model.
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