The Semiconductor Technology Academic Research Center (STARC) is ready to recommend design rules for System on a Chip (SoC) ICs fabricated with the most advanced 0.13um semiconductor processes. The design rules consist of 2D layout rules and SPICE device model parameters.

    The relentlessly advancing deep sub-micron semiconductor process technologies now enable the integration of millions of transistors on a single chip, enough for development of SoCs. The maximum reuse of existing designs, termed IP or VC (virtual component) is indispensable to successful SoC business, which is under severe time-to-market competition pressures. And it is essential for the SoC industry to promote circulation and reuse of VCs within companies and among companies.

    However, semiconductor manufacturers have developed different sets of process technologies to maximize performance, yield and profitability of their own products. This process divergence makes VC reuse-based SoC design difficult and time-consuming because SoC designers need to convert different mask design rules to their own processes and verify the results by DRC checker and even on real silicon. Also, verification of performance and yield for the derivative VC is a difficult, time-consuming and error-prone task.

    There is a great help to reduce these difficulties if SoC industry has an open standard for 2D layout rules and SPICE device model parameters for specific process generation. STARC worked with Japanese semiconductor manufacturers to examine and evaluate various 2D layout rules and SPICE device model parameters for advanced 0.13um processes. From this work STARC developed and specified its new design rules, which will be open to the SoC industry as the STARC recommend SoC design rules.

    The new design rules can deal with the most advanced SoC process worldwide, while at the same time it adapts to process deviations among various semiconductor manufacturers. Hence, STARC believes their SoC design rules can be adoptable by most semiconductor manufacturers without major process problems.

    STARC will reveal its recommend SoC design rules worldwide. The company looks forward to their wide adoption not only by the semiconductor manufacturers but also by companies in related industries, such as the library vendors, VC providers and system design houses.