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| Open Program |
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Japanese
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STARC continues the three main activities that have been conventionally performed in its core program, namely joint research with universities, education and prototype fabrication support, and based on these activities, promotes research and development activities with "I. Application Market Expansion," "II. Design value improvement," and "III. Design Productivity Improvement" as the three pillars of the open program.
The areas/scopes of our activities are the development of design-related (including software) technologies, product design for demonstration, IP design, software development and the development of new applications. They are also divided into three categories according to their objectives and targets: the expansion of the semiconductor market (Cooperation with application industry), advancement of design value, and improvement of development efficiency. In particular, Cooperation with application industry is a new program to undertake and we will also cooperate with semiconductor users to expand the field of application of semiconductor products. In addition, we will extend the scope of the program to allow more open participation and invite non-shareholding companies. |
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| I. Program for market expansion <inter-application, exploration/analysis and leading research> (Planning Department) |
| With the aim to expand the application area of semiconductor products, we will explore and analyze the needs, promote standardization for semiconductor products in demand, and propose new technologies, in collaboration with inter-application (with semiconductor users). The areas we will focus on first are life innovation (health care and medical care) and green innovation (environment). |
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| II. Program for advancement of design value <extremely low-power circuits and systems project> (R&D Department-1) |
| While it is urgent to take measures against global warming, an explosive increase in power consumption is prospected due to the use of various information devices. It is accordingly necessary to reduce power consumption of all electrical devices including servers, information terminals and home appliances. This project is aimed at "Green of IT". And with the technologies achieved through it, it will also contribute to "Green by IT". To this end, we will develop logic, memory, analog, power supply, and radio circuits and system technologies with the target of reducing the power consumption of LSI to one tenth of the current level. While the decrease of power-supply voltage to an extremely low level (0.5V or less) is an efficient method for the reduction of power consumption, this requires measures against variance and there are other problems to be solved. We have organized an academic-industrial collaboration project with universities to promote research and development to meet this challenging target. <Commissioned by NEDO> |
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| III-1. Program for the improvement of development efficiency <cool chip design project> (R&D Department-2) |
(1) Development of technologies for system LSI analysis: LSI process has been miniaturized to 28nm and then to 22nm, and LSI design requires "improvement of design efficiency in response to further increase in the scale of circuits," "achievement of a high precision analytical environment that corresponds to higher speed and lower voltage," and "identification of and response to phenomenon in device characteristics with 28nm or below process" as the element technologies. The development of these technologies determines the success or failure of the future system LSI business. Sharing risks and costs with associate companies on these technologies in advanced technology nodes, we will develop methodology to strengthen international competitiveness in the industry.
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(2) Development of mixed signal design technology: The miniaturization of the process has resulted in longer time for analog design. STARC successfully reduced the time for design by half in two years from 2009 to 2010 through the development and establishment of STARCAD-AMS (Note), which solves the problems mainly caused by layout design. In the future, we will expand the area of development and satisfy the requirements of the actual design site for the reference flow such as the realization of analog/digital codesign, the determination of reuse methodology, and further reduction of TAT.
(Note) AMS: Analog-Mixed-Signal
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(3) Development of multi-chip design technology: With more sophisticated system requirements and miniaturized processes, the limits of one-chip solutions are becoming clearer. To respond to "More moore" and "More than Moore," it is now essential to develop new solutions with 3D-IC design technology based on Packaging technology. STARC will develop the design methodology technology integrating the net assignment technology using cooperative planning, modeling technology for analysis, and the technology to integrate the analytical databases that are different between LSI, packages and boards as the element technologies necessary for the 3D-IC design technology.
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(4) Joint evaluation of EDA tools: While the use of EDA tools is essential due to the complexity of LSI design, it is inefficient to assess new of revised EDA tools company by company. STARC therefore performs joint assessment and shares the results to reduce the assessment cost
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| III-2 Program for the improvement of development efficiency <promotion of the use of HiSIM (Note)> (R&D Department-2) |
III-2 Program for the improvement of development efficiency <promotion of the use of HiSIM (Note)> (R&D Department-2)
We will promote the methods to improve and use the models of HiSIM-HV and HiSIM2, which have been officially certified by the Compact model Council (CMC), in coordination with Hiroshima University and member companies.
(Note) HiSIM: Hiroshima-University STARC IGFET Model
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| III-3 Program for the improvement of development efficiency <next-generation TCAD platform> (R&D Department-2) |
We will develop a next-generation TCAD platform, which is the physical simulation technology that connects circuit design technology and device technology in order to enhance the total design technology covering system design, devices and production.
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| III-4 Program for the improvement of development efficiency <promotion of standardization of STIL> (Planning Department program) |
We will promote the improvement of the efficiency of device tests through cooperation with semiconductor manufacturers and tester manufacturers for the standardization of a test program.
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