Tokyo - August 14, 2001.
STARC (Semiconductor Technology Research Academic Center, President Kunio Hasegawa: http://www.starc.jp) and its twelve member companies(*2) have agreed to launch the STARC standard for IP-based SoC design technology set for 100 nm generation. This agreement intends to strengthen SoC design by focusing on strong IP reuse technologies not only for individual companies but also for the whole SoC industry, including semiconductor manufactures, IP providers, System houses and EDA tool suppliers.
The STARC IP-based design technology set includes (1) technical infrastructures such as the design style guide and IP trading standard, (2) common design rules of 2D geometries and SPICE parameters, (3) IP libraries. STRAC and its twelve member companies agreed to promote the technology set throughout the SoC industry to make IP trade and reuse much more efficient among the adopting companies.
Next Step
Twelve STARC member companies have agreed to share the IP based SoC design technology set as the technology standard for their 100nm SoC design. These companies will continue to develop technologies and infrastructures both alone and together to improve SoC design efficiency with inter industry-wide IP-reuse. The adopters believe the STRAC standard is of major benefit to their businesses, because the standard enables them to focus more on their core competence by reuse of outside technologies much more efficiently.
This is the first result of the JEITA ASUKA(*5) project that focused on most advanced 100nm to 70 nm semiconductor technology developments in Japan.
STARC is committed to enhance the standard and open it to be a true worldwide de-facto standard.
Background
Ultra deep sub-micron semiconductor process technology enables the industry to build tens of millions of transistors on a single chip to create a true system-on-a-chip. These SoCs have been major sources for the innovation of social infrastructures, scientific achievements, amusements and so on. Therefore, it is a fundamental necessity for whole industries to challenge innovation to make SoC more affordable.
By its nature, SoC includes a large number of heterogeneous functions. It is extremely important to improve design efficiencies in building SoCs to keep up with market demand. The importance of intra-industry and inter-industry IP trade and reuse is widely recognized in efforts to make SoC design efficient.
In reality, various technical and business obstacles exist. One of the major obstacles is the difference of the process technologies among SoC manufacturers, even in the same process generation such as 100nm. SoC design efficiency suffers because these process differences make IP reuse without modification and re-verification almost impossible. It is very important to establish a reasonable common standard among these semiconductor manufacturers to enable IP reuse without or with minimal modification and re-verification.
STARC and its twelve SoC manufacturing member companies have been working together to conquer this difficult challenge. They have achieved several milestones in their IP-based SoC design technologies; such as STARC SoC design style guide (July 2000)(*3), STARC 130nm common design rule (September 2000)(*4). With these achievements, they have enhanced the STRAC standard for the STARC recommended IP-based SoC design technology set that is additionally includes the physical, electrical design rules for 100nm process and the cell libraries matching with the 100nm design rules.
STARC will continue to work as a foundation for the development and sharing of the various design methods, technologies, and IP, such as embedded processors, that help the design of IP reuse-based SoC more efficient, productive and affordable.
For More Information, Contact:
Mr. Tadahiko Nakamura
General Manager, IP Technology Development Group, STARC
Tel: 045-478-3260 (Japan)
E-mail: [email protected]
Mr. Takahide Inoue (U.S.A)
Consultant for IP Technology Development Group, STARC
Tel: 510-658-2633 (U.S.A)
E-mail: [email protected]
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*1) STARC: Semiconductor Technology Academic Research Center. http://www.starc.jp
*2) STARC member companies:
*3) STARC SoC design style guide: English version available from H.D Lab Inc,
http://www.hdlab.co.jp
*4) STARC 130nm common design rule: Information available from http://www.starc.jp
*5) JEITA ASUKA:
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