Links
StatusFuture Works
Data
Last update: 2002/05/27
Status
| Second Half of 2001 Fiscal Year | ||||||||||||||||
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STARC opened "e" Temporal Language Reference (STARC Ver.1.1) as recommended Interface Specification Language @ SoLID. (2002.4) [SoLID Data area ...] Scripts using on logic synthesis are investigated as Target Specification Description. The description of design restrictions is classified into "external condition of IP (Environmental Constraints, example: arrival time and transition probability of input signal)" and "design target of IP (Objective Constraints, example: operation frequency and power consumption on peak time)", and SDC (Synopsys Design Constraints) was considered as description for Target Specification covering the domain of timing, area, power, and SI respectively.
We clarify Design Target Specification Description focusing on SDC, and how to give the restrictions information for the power and the layout which are not defined in SDC. | ||||||||||||||||
| First Half of 2001 Fiscal Year | ||||||||||||||||
| Among these, the compliance test of "e", which became the first candidate, using real design data was performed to describe the functional and timing operation of IP. We confirmed enough capability of "e" language of Interface Specification Description for functional verification. | ||||||||||||||||
| Second Half of 2000 Fiscal Year | ||||||||||||||||
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It became clear that description of temporal logic, which describes temporal relationship between events, is mandatory for Interface Specification at that stage of drawing up the requirements for Interface Specification Language.
We evaluated the languages proposed from EDA venders, which can describe such temporal logic, based on the allocation of score table created referring to discussions in Formal Verification Technical Sub Committees at Accellera in terms of the requirements for Interface Specification Language.
As a result of scoring, STARC chose candidates of recommendation "Interface Specification Language", which expresses intentions of design, for doing the compliance test of IPs. First candidate is "e"(Verisity), and second candidate is "xOwL"(Hitachi). | ||||||||||||||||
| First Half of 2000 Fiscal Year | ||||||||||||||||
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Elements for describing functional verification items were summarized by analyzing the functional verification specifications of STARC member companies. We drew up requirements for Interface Specification Language, based on the elements of functional verification. (This requirements document will be opened soon at [SoLID Data area] to STARC members only.) | ||||||||||||||||
Future Works
- Compliance test which changes RTL of soft VC using SoLID to a layout
- Propagation of Interface Specification Description Language - release of protocol monitors for common buses (AMBA(AHB, APB), PVCI)
| Copyright (C) 2002 Semiconductor Technology Academic Research Center(STARC) |