OverviewTopic
Status
Future Works
Data
Last update: 2003/02/14
Overview
In order to distribute design information of "Common Design Rule", which is design infrastructure for IP (Intellectual Property) reuse, widely without ambiguity, STARC is developing design rule description language (DRML: Design Rule Markup Language). DRML provides the function of both the design rule for investigating to know, and the design rule for using as input file of EDA tools with preparing GUI and API, and realizes to construct electrical database of design data unified management and efficient design environment.
- DRML based on XML can describe all information of the design rule manual by the optimized tags. 2-dimensional size in the design rules, electrical parameters, process parameters and mask creation specification are described.
- DRML performs description of the design rules corresponding to circuit blocks, such as CORE, I/O and SRAM, effectively. Its capable to reuse and simplify the description when the design rules of fifth level of interconnect metal layers are the same as the fourth level, because of the optimized hierarchy of DRML.
- Display of usual spreadsheet form and layout figure are changed simply using tabs on GUI. Display focusing transistor pitch of the design rules, and display as cross sectional view of the interconnects will be performed in near future.
- DRML can be automatically translated into input files for various EDA tools by preparing API. DRML also supports priority tag to control only translating easy design rules into "Real Time DRC" tool.
- By using DRML, it becomes unnecessary to correct and manage various rule files for design and verification, and it is not so difficult to realize extended function having revision history.
- Use on the network and reuse of the description are also excellent.
| Copyright (C) 2002-2003 Semiconductor Technology Academic Research Center(STARC) |