1.
Overview
2. Activities
3. Topics
4.
Link
|
Last update: 2002/04/02
1. Overview
- IP reuse is indispensable for SoC design productivity improvement.
- But, IP reuse is not activated actually due to the lack of a common
process technology that different companies abide by. This is the reason
why the common technical foundation is required.
- IP reuse group is tackling the constitution and the promotion of a
technical standard used as the common technical foundation in a design
rule and cell library aiming at increasing IP reuse and trade among the
different companies.

2. Activities
- (a)Constitution of Common Design Rules
- The technical standard of 2D geometries and SPICE parameters is
enacted. Thereby, (1)the performance and characteristic of IP can be
estimated, (2)the dedicated process can be developed in the process
based on common design rule, and (3)the cooperation in a process and a
design development can be performed.
(b)Development of Common
Libraries
- We are developing the cell library including standard cells, I/O
cell, SRAM, etc. In the course of development, sharing the information
such as a cell naming rule, etc. is promoted. This rule is expected to
promote the sharing of IP among the companies.
(c)Promotion of
Global Standardization
- We aim at that common design rule and library spreads widely into the companies
other than our member ones. These companies include IP vendor, EDA vendor,
fabless company. You can receive STARC open "Design Rules for 0.1
micron" by concluding a disclosure statement. For details, please
see the acquisition method.
3. Topics
- (2001 Oct.)
- Presentation at VSIA Member Meeting
- (2001 Aug.)
- Announcement of STARC recommended "Common Design Rules and
Cell Libraries for 0.1 micron"
- (2000 Sep.)
- Announcement of STARC recommended "Common Design Rules for
0.13 micron"
4. Link
(not available)
|