OverviewLinks
Status
Future Works
Last update: 2002/05/27
Overview
Reuse of IP is import of other designer's knowledge as a black-box. However, IP cannot be used without understanding functional and timing operation of IP. Usually, "knowledge of IP provider" is delivered to IP user in form of "specification manual of IP operation" and "comments in hardware description." Although IP user must understand these information enough, it becomes the drawback of IP reuse, since such design spends extensive time and does not guarantee to cover functional verification in detail.
Then, "knowledge of IP provider" is defined as a data package of descriptions (SoLID: STARC open Language for Intention of IP Data), which can be read by EDA tools and are eliminated ambiguity as much as possible by changing into IP descriptions with direct expression of specification and intention of designer from descriptions of conventional tool operation. In addition, these formats are standardized. Consequently, reduced time of design and endorsement of operation are realized by using the black-box IP with SoLID.
When IP is soft VC (Virtual Componet), the data package SoLID is divided roughly into the portion describing what specification IP has, and the portion describing how it integrates.
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Download Interface Specification Description and Target Specification Description
Interface Specification Description is indispensable information in order to express the functional and timing operation of IP and integrate IP into user design correctly. The violation can be automatically detected during functional verification simulation, if usage of IP is incorrect against the operation describing Interface Specification Description. Test Program Description is the scheme for functional verification and timing verification.
Another is description of how to convert the circuit (RTL) including IP into gate level and layout level data maintaining the specification of IP. Target Specification Description describes the target performance on integrating, such as a clock frequency. EDA Tool Command Specification Description describes the hints of design, such as scripts for logic synthesis tools and circuit structure for achieving the target performance.
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