System-Level Design Automation Technologies

<body bgcolor="#ffffff" text="#000000" link="#990000" vlink="#990000" alink="#ff0000"> <p><a name="vcdsgr-e-0"></a></p> <table border="0" width="100%" cellpadding="0" cellspacing="0"> <tbody> <tr> <td align="center"></td> </tr> </tbody> </table> <p><a name="vcdsgr-e-1"></a></p> <table border="0" width="100%" cellpadding="10" cellspacing="1" bgcolor="#990000"> <tbody> <tr> <td background="http://www.starc.jp/kaihatu/vcdsgr/image/back.gif"><font color="#ff0000"><b>What's New !</b></font> <ul> <li>January 29, 2003: <b>Conference presentations updated</b> </ul> </td> </tr> </tbody> </table> <p><a name="vcdsgr-e-2"></a></p> <table border="0" width="100%" cellspacing="0"> <tbody> <tr> <td bgcolor="#fdd5e0"><b>VCDS Development group overview</b></td> </tr> <tr> <td height="2" bgcolor="#a80259"></td> </tr> </tbody> </table> <blockquote><b>VCDS: Virtual Core based Design System</b></blockquote> <blockquote>    The VCDS development group was organized in April 2000. The mission of our group is the research and development of advanced design technologies to drastically increase the design productivity of large scale system-on-chip (SoC).<br> <br>     The research and development of the Virtual Core based Design System is currently done by a team of 28 researchers. They come from the 12 client semiconductor companies, EDA vendors, and software houses as temporary assignees.<br> <br>     Starting from the year 2000, the 5 year NEDO entrusted project "Research and Development of Advanced Design Technology for SoC" aims at developing the basic VCDS technologies. The "Asuka Project", started from the year 2001 aims at integrating the developed basic technologies into a novel SoC design system.</blockquote> <p><a name="vcdsgr-e-3"></a></p> <table border="0" width="100%" cellspacing="0"> <tbody> <tr> <td bgcolor="#fdd5e0"><b>VCDS Development</b></td> </tr> <tr> <td height="2" bgcolor="#a80259"></td> </tr> </tbody> </table> <ul> <li>October 2002:<br> <b><a href="../../../vcds/vcds021107_e.pdf" target="_blank">VCDS Technology presentation (PDF file)</a></b> </ul> <ul> <li>January 2002:<br> <b><a href="../../../kaihatu/vcdsgr/vcds_intro_e/4nofrm/" target="_top">VCDS presentation panel for EDS2002 (Yokohama)</a></b> </ul> <ul> <li>September 2001:<br> <b><a href="../../../kaihatu/vcdsgr/project_e/2nofrm/" target="_top">NEDO project "Research and Development of Advanced Design Technology for SoC" contents and goals (pamphlet)</a></b> </ul> <p><a name="vcdsgr-e-4"></a></p> <table border="0" width="100%" cellspacing="0"> <tbody> <tr> <td bgcolor="#fdd5e0"><b>Press Releases</b></td> </tr> <tr> <td height="2" bgcolor="#a80259"></td> </tr> </tbody> </table> <ul> <li>June 12, 2001:<br> <b><a href="/" target="main">Entrusted NEDO's "Research and Development of Advanced Design Technology for SoC" project press release</a></b> </ul> <p><a name="vcdsgr-e-5"></a></p> <table border="0" width="100%" cellspacing="0"> <tbody> <tr> <td bgcolor="#fdd5e0"><b>Conference presentations</b> </td> </tr> <tr> <td height="2" bgcolor="#a80259"></td> </tr> </tbody> </table> <ul> <li>January 23,2003:<br> <b>ASP-DAC'03: ?iInvited?@Talk?j?gVCore-based Design Methodology?h [Kitakyushu /Japan]<br> ASP-DAC'03: ?iInvited?@Talk?j?gSynthesis for SoC Architecture using VCores?h [Kitakyushu/Japan]<br> ASP-DAC'03: ?iInvited?@Talk?j?gVCore-based Platform for SoC Design?h [Kitakyushu/Japan]<br> ASP-DAC'03: ?iInvited?@Talk?j?gVCDS Tool Demonstration?h [Kitakyushu/Japan]</b> </ul> <ul> <li>November 22, 2002:<br> <b>WRTLT'02?F"A Test Plan Grouping Method to Reduce Test Length and Test Controller Area for RTL Data Paths" [Guam/USA]</b> </ul> <ul> <li>November 21,2002:<br> <b>WRTLT'02?F"A Non-scan DFT Method for RTL Data Path Circuits with Various Bit Width" [Guam/USA]</b> </ul> <ul> <li>November 19,2002:<br> <b>ATS'02?F"A SoC Test Strategy Based on a Non-Scan DFT Method" [Guam/USA]</b> </ul> <ul> <li>November 18, 2002:<br> <b>ATS'02?F"A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique" [Guam/USA]</b> </ul> <ul> <li>May 1, 2002:<br> <b>VTS 2002 : "A Test Generation Method using a Compacted Test Table and a Test Generation Method using a Compacted Test Plan Table for RTL Data Path Circuites" [Monterey, CA, USA]</b> </ul> <ul> <li>January 11, 2002:<br> <b>46th FTC: "A Non Scan DFT Method Using Functional Information of Operational Modules" [Kumamoto, Japan]</b> </ul> <ul> <li>January 10, 2002:<br> <b>46th FTC: "A Test Generation Method Using a Compacted Test Plan Table for RTL Data path Circuits" [Kumamoto, Japan]</b> </ul> <ul> <li>November 23, 2001:<br> <b>WRTLT '01: "A Compacted Test Plan Table Generation Method for RTL Data Path Circuits" [Nara, Japan]</b> </ul> <ul> <li>November 22, 2001:<br> <b>WRTLT '01: " A Non Scan DFT Method Using Functional Information of Operational Module" [Nara, Japan]</b> </ul> <ul> <li>November 22, 2001:<br> <b>WRTLT '01: "VCore Based Design Technolog for the Next Generation" [Nara, Japan]</b> </ul> <ul> <li>March 27, 2001:<br> <b>IEICE General Conference: Tutorial [Kusatsu, Shiga, Japan]</b> </ul> <ul> <li>March 5, 2001:<br> <b>IPSJ RTP 2001 : Invited Talk on "VCore Technology and VCDS Project" [Nara, Japan]</b> </ul> <hr width="80%" noshade> <p align="center">Updated at February 6, 2003<br> <a href="mailto:info@starc.or.jp"> E-Mail : info@starc.or.jp</a><br> <font size="-1">Copyright (C) 2001-2003 STARC</font></p> </body>