High-level Design Development Department
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| Updated information |
The top page of the High-level Design Development Department has been renewed
(February 23, 2004).
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| Summary of the High-level Design Development Department |
High-level Design Development Department - Summary
This development department is involved with the research and development
of high-level design methodologies, as well as design automation technologies
for system, architecture and software levels, in order to improve the design
efficiency and to optimize the design of the SoC, which is becoming increasingly
larger in scale.
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Current research and development
The department is proceeding with research and development with the aim
to provide solutions for the issues relating to the existing high-level
design of the SoC.Further, development of the gHigh-speed Coordinated
Verification Technology for Hardware and Softwareh is being promoted as
a new technology.
The coordinated verification technology that can be used to verify the
overall system by bundling together both the software and hardware in a
single unit, is becoming more and more important with the current System
on Chip (SoC) designs.
Verification of the overall systems, however, has been difficult to realize
with coordinated verifications based on the existing Instruction Set Simulator
(ISS), as the verification speed is much too slow.
This development department is researching and developing high-speed coordinated verification technology, targeting 107 to 108 commands per minute, which is approximately one thousand times faster than the rate available with existing technologies. With this technology, it will be possible to see a vast improvement in the efficiency of the coordinated verification of hardware and software.
High-level design development technology
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| Development technology |
High-speed coordinated verification technology
Purpose: Realization of an advanced software verification environment.
- Targeted performance: 107 to 108 commands per second (one thousand times faster than the existing performance rate).
- A new methodology that does not involve an Instruction Set Simulator
(ISS).
- Hardware will be the Transaction Level Modeling (TLM).
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| FAQ |
| The gVCDS Demonstration (limited features edition prototype)h CD-ROM
cannot be played. |
The Proper playing of animated images is not possible unless a Quick Time
Player is installed in the computer being used. Please install the Quick
Time Player according to the procedure described below:
(1) Once the automatic playing of the CD starts, press the [ESC] key to
escape from the playing process.
(2) Open the CD with a single click on the icon of the CD drive with the
right mouse button (double clicking will start the playing).
(3) Follow the instructions in the gReadme.txth file provided on the
CD to install the QuickTime.
The latest version of the software can be downloaded from the following link:
Latest version of Quick Time Player download
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| Contact |
| Please forward your opinions and feedback on this web page, to the following
address: |
Semiconductor Technology Academic Research Center (STARC)
6th Floor, Yusen Shin Yokohama Building3-17-2 Shin-Yokohama, Kohoku-ku,
Yokohama, Kanagawa 222-0033, JAPAN
TEL: +81-45-478-3300 (Switchboard)
FAX: +81-45-478-3299
E-Mail: [email protected]
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