Introduction to PhD-Group
Three Working-Group activities and members


TEG Sub Gr. (Variability/Yield , RF)
Major topics of TEG-Gr are SoC performance variability-design, process/performance yield analysis and optimization, and their Data-Base development. We focus on fact-finding on these issues by developing special Large-Scale Test Structures, which may become world-standard TEGs in lumping-up VDSM processes. Based on these activities, we hope to build a new venture business model from STARC.
RF circuit design is updated topic in Mobile communication SoC. Our group focuses RF modeling of active device (MOS) and passive elements (C,R,L).
Test structures of these RF-components and RF circuits are major concern in the modeling & verification research & development works.
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Modeling Sub Gr. (Interconnects)
Major topics of this Modeling-Gr. is interconnect-model for circuit simulation.
In interconnect modeling, a high-speed inductance extraction and simulation system have been newly proposed and under development. Objective of our Group is world-top-level modeling activities in VDSM Physical Design Modeling including Signal-Integrity design.
A new Interconnect Architecture has been proposed and now under development to solve major SI problems such as cross-talk, power-bounce and inductive noises.
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Modeling Sub Gr. (HiSIM/Benchmark)
New physical-based MOS Compact MODEL (HiSIM) has been developed in STARC & Hiroshima-U. Joint-project. In our group, the model improvement and user-support are conducted.
In Benchmark, new innovation in EDA benchmarking methodology is one of the major roles, in Physical Design area. Layout (P&R), Timing Closure and Signal Integrity are one of the largest topics of our interest. We cooperate with many active vender and bencher companies, to consolidate the benchmarking methodology, with open test structure strategy.
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