Mission:
|
Mission:
|
| Researchers: |
|
| K. Morikawa |
STARC Proper: It is exciting for me to work at the STARC Physical Design Group, with expert engineers who join from many semiconductor companies. I hope to contribute in the area of fruitful TCAD-ECAD solutions, based on my modeling reseach in deep submicron MOSFETs, in the very near future. |
| HiSIM is Collaborated World-Wide Activity on a New Compact MOS Model, promoted
by STARC R&D Dept. & PhD Modeling-Gr. and Hiroshima -University. |
| HiSIM Update HiSIM is promising and inevitable compact MOS model in VDSM era. Major contribution of HiSIM is world-first practical Physical-based variability design capability. VDSM process parameters can be linked directly to MOS performance through HiSIM, which allows designer accurate statistical and worst corner design with least conservative manner. STARC has joined Compact Modeling Council since Dec. 2002, to promote and develop more reliable improvement of HiSIM with Tool Venders and Fabs, Design House, together. CLICK Here for Automatic Compact-model Benchmarking (pdf 97KB) CLICK Here for Updated Status (pdf 1040KB) |
| SI (Signal Integrity)-Related Benchmarking Design House engineers and EDA-tool vender people wish to establish tool benchmarking standard and methodology. We propose new SI-related tool benchmark cite for such people. STARC-TEGs have been designed annually and fabricated chips, with updated CMOS process, were carefully measured by STARC. All the design data and experimental data are open for the engineers of Design Houses and EDA-venders. All people can download the GDS2 and Experimental-Data without any restriction, for the purpose of fair use of these data. Some benchmark example have been conducted as cooperation work of STARC and EDA-Venders. CLICK Here for STARC Benchmark Style (pdf 20KB) CLICK Here for statistical Benchmark Methodology (pdf 142KB) |
| (1) Power-Net SI Tools: Benchmarking One of the SI issues which cause trouble in physical design is Power-net bounce problems in high-speed processor and/or SoC. Various analysis tools are available, however, no one Silicon proven. We designed a series of TEG for the Power-net bounce problems and measured with special on-chip circuit. Based on this experiment, we conducted benchmarking of an EDA-tool with reference-tool (SPICE) simulation results. The GDS2 and necessary process information are available under NDA. Correspond to E-mail: [email protected] CLICK Here for Benchmark Example (pdf 221KB) CLICK Here for Benchmark Manual (pdf 43KB) |
| (2)Cross-talk SI Tools: Benchmarking X-talk noise/delay is another concern of the SI issues which cause trouble in physical design and SoC timing closure. Various analysis tools are available, however, no one Silicon proven. We designed a series of TEG for the X-talk noise/delay problems and measured with special on-chip circuit. Based on this experiment, we conducted benchmarking of an EDA-tool with reference-tool (SPICE) simulation results. CLICK Here for Benchmark Example (pdf 193KB) CLICK Here for Benchmark Report (pdf 945KB) |
New Compact Transistor Model (HiSIM)