Mission:
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Mission:
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| Researchers: |
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| A. Maruyama |
From Rohm: |
| Chip-level Yield/Variability TEG For methods of optimizing the physical design of SoCs (system on a chip), the evaluation of yield and variation is important to achieving finer structures, higher integration scale and higher precision. Here, we report on the first development of a TEG (Test Element Group) that has large-scale patterns that compare well to those of SoC. This TEG is based on the design rules of pure processes that are independent of the product for determining yield, defects, and defect locations and for evaluating characteristic variation. Another feature is that it has dedicated address decoders in the four corners. Our objective is a TEG that can acquire data on yield and defects and on statistical variation that will facilitate innovation in conventional optimum design methods. In this regard, we have developed a program for use with a logic and memory tester to do automatic measurement at the fabrication plant. We are aiming for a TEG that will serve as the core of strategic technology for increasing development efficiency and will promote standardization by integral linking of design, fabrication, measurement and evaluation. To this end, we will use it in combination with electrical measurement methods for the relevant dimensions, evaluation methods for charge-up damage, and analysis database software. CLICK Here for Electrical Physical-value Measurement TEG (pdf 164KB) Information for Yield TEG: Coming soon |
| DMA(Device Matrix Array) Inter-Chip Variability TEG For future LSI design technology, the Device Matrix Array (DMA), which precisely evaluates the variation of device parameters within a die, has been developed. The DMA consists of common units (14 x 14 arrayed with 240um pitch), each containing 148 elements of transistors (Tr), resistors (R), capacitors (C) and ring-oscillators. The leakage reduction circuits and hierarchical bus architectures enable to obtain the measurement accuracy of 90pA(Tr), 11mƒ¶(R) and 23aF(C) in 3ƒÐ range and the spatial resolution of 240 um in the 4mm x 4mm area of the test chip fabricated by 0.13um-CMOS process. CLICK Here for DMA-TEG Information (pdf 29KB) |
| RF Component & Circuits TEG RF circuits are one of the key technologies in communication LSI with their frequency range of GHz. We focus detail high frequency characterization of devices such as MOSFET, Spiral Inductor and Capacitor as on-chip component. Modeling and simulation technique is our interest with circuit simulator and Electro-Magnetic simulator. Measurement at high frequency range of the components is the bases to conduct development of RF-ICs. CLICK Here for Spiral Inductor TEG and Simulation (pdf 264KB) CLICK Here for Substrate Noise transfer TEG (pdf 205KB) |
Test Structure Develop. for Variation & Yield Design