Mission:

　Signal Integrity TEG and Modeling

　DSM Interconnects Library and Model Parameters

　On-chip LCR Extraction and Simulation

　Chip-level Power Net Analysis

　New Interconnect Architecture






Researchers:
T. Kage

From Fujitsu:
In PhD-Gr., researchers with various excellent backgrounds are working together. I enjoy working with such peoples, on the topics of Modeling and Benchmarking in Physical Design area. Hoping to give new evolutive & innovative contributions in PhD.





A. Kurokawa

From Sanyo:
My research interests are in the design automation of VLSI circuits, especially modeling and avoidance of signal integrity, on-chip inductance extraction, and low-power design method.Hoping to develop new design methodology.





K. Nagase

From Sharp:
In a sub 100nm technology, analyzing device
characteristic variation quantitatively and
modeling it as circuit performance variation is
expected as the design for manufacturability(DfM).
It is a goal in my STARC activity to carry out
effective technical establishment in this DfM
technical field.






N. Sumiyoshi

From Rohm:
My special field of study is High Speed Serial Design.
In addition, I am interested in RF-PAN.
I think it can play an active part in starc from such viewpoints.






Topics


PowerSpective and LiCRSIM:is Collaborated Activiyt on a New Chip-level LCR Extractor and Linear Simulator, promoted STARC and Mathematical Systems Inc.

CLICK Here for Research Activity Overview (pdf 144KB)
CLICK Here for LCR-Extractor and Simulator (pdf 528KB)


STARC-SPICE:is Collaborated Activity on a HiSIM & HC-Degradation Models implemented into a CKT-Simulator, promoted by STARC and
Hitachi ULSI Systems Co. Ltd.


ILDEx:is Collabolated Ativity on a New Inter-Layer Dielectric Extractor With Special Test-structures, promoted by Fuji Research Institute Co.

CLICK Here for Inter-Layer-Dielectric Parameter Extraction Tool (ILDEx)
(pdf 102KB)
CLICK Here for Interconnects Capacitance Extraction TEG (pdf 359KB)



Interconnect High-frequency Characterization

To probe new insight of a 130nm Process-node Cu-Interconnects, we focus on high frequency characteristics up to 5GHz clock range. Series of test structures are designed for S-parameter measurement to evaluate their Transmission-Line effects. Significant inductive component with strong frequency dependent has been proven. In on-chip interconnects, power lines found to be anymore the ideal current return path, which result in heavy frequency dependent roop-L & R. It is also predicted that the inductance (L) shows comparable delay element as CR-delay at 1GHz signal transition. Most important feature in interconnect design, however, is their die-to-die variation found to be well above 10% in 2s, suggesting the increased importance of interconnect worst-case design methodology, in 130nm CMOS.

CLICK Here for Interconnect S-para measurements and Modeling (pdf 107KB)



A New Interconnect Architecture (Coming soon!)

Timing closure is critical physical design issue for updated process and SoC. Xtalk, Power net noise and inductance effects are all the key topics which make physical design closure difficult. These physical phenomena come from scaled interconnect characteristics. In nm process, Lithography is biggest red block technology also to define minimum feature size of wires. CMP and PSM process has been developed to achieve high resolution technological solution.

We have proposed and under development of a novel interconnect architecture witch perfectly fits to achieve Signal-Integrity free and ithography friendly interconnects.



Gate-level Timing Model & Variability Design (Coming soon!)

Solution of timing closure problems is to develop Gate-level timing model and EDA tool implementation, which can handle statistical and/or worst-case corner design style.
Based on the STARC-TEG experimental data-base, we have started the research and development work on these topics especially focused on physical design issue.
This comes up soon!