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January 2002
Semiconductor Technology Academic Research Center (STARC)
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STARC and Osaka University
develop high-speed design technology for embedded ASIP
Education-use ASIP design tool "ASIP Meister" released
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Education-use ASIP Meister released
STARC and a research team led by Professor Masaharu Imai of Osaka University have developed a next-generation high-speed design technology for embedded processors and commercialized it as a design tool for educational use.
The new technology is a fast design method for application-specific instruction-set processors (ASIPs) embedded in systems-on-chip (SoCs). Binary codes of the ASIP Meister, a tool for teaching ASIP design based on the new method, will be distributed free of charge to universities and other academic institutions beginning in April 2002. The joint research team will exhibit the tool at the Electronic Design and Solution (EDS) Fair 2002 at Pacifico Yokohama on January 24.
Current status of embedded processor design
In the past, processor design was the preserve of highly skilled and specialized elite engineers known as computer architects (hence Meister-German for “master of a trade”). Moreover, commercially available processors were usually chosen as embedded processors because of the huge number of processes required to design one from scratch.
However, general-purpose processors on the market are not necessarily the best solution in terms of all-round capability (performance, cost and power consumption). Moreover, there is constant demand for specific-purpose processors that provide superior performance in hi-tech applications such as multimedia and broadband. There is also a requirement for processors with low power consumption for battery-operated devices like cellular phones and PDAs. ASIPs offer a solution to these problems.
Effectiveness of ASIP Meister
ASIP Meister is an innovative design tool for embedded processors with a pipeline architecture. It is claimed to increase the design productivity of embedded processors more than 100 times compared with existing design methods. For example, a MIPS R3000-class RISC processor can be designed in about eight hours using ASIC Meister. Selection of functional components used in the processor core and changes to instruction sets can be made in a short time, enabling high-speed design optimization that takes into account the trade-off between performance and chip size.
ASIP Meister not only enables high-speed design of new processors, but also the utilization of a company’s valuable design assets and know-how to design derivatives. Further, users can use ASIP Meister to design their own ASIPs to their own specifications, liberating them from payment of expensive royalties required when buying in an existing processor core as intellectual property.
ASIP Meister as an educational tool
In the past, the sheer length of time required to design embedded processors created a bottleneck in educating students about processor architectures, but with its fast processor design capability, ASIP Meister offers an ideal training resource for students in both classroom and laboratory settings.
STARC plans to use ASIP Meister to promote education in SoC design for students as well as IT professionals to raise the standard of SoC design, with the ultimate goal of strengthening Japan’s design technology and propelling the country to a world-leader position in this field.
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