In the VDSM (Very Deep Sub-Micron) era, Physical Design of VLSIs becomes one of the major issues for successful SoC (System on a Chip) products. Time-to-Market, it is also the continuous challenge in Semiconductor Industry.

Objective of STARC “Physical Design Group” is to develop new technology and methodology in VDSM physical design issues, such as SI (Signal Integrity) problems, optimized (compromised) variability design method and quick yield-ramping. Fact-finding on wafer is our approach, therefore, well-devised Test Structures (TEG: Test Element Group) for updated process (0.07-0.13um CMOS) are our big challenge against the VDSM physical design issues.

“Physical Design Group” has three aggressive Working Task-Forces to achieve world’s top level design technology development.

Slides on Mission and Activities of PhD Gr.;

2000-2001 (pdf 1093KB)

2002 EDS-Fair Panel (pdf 740KB)

2002 (pdf 1598KB)

2002 SoC Forum (pdf 2208KB)

Special Projects

HiSIM (Updated) is Collaborated World-Wide Activity on a New Compact MOS Model, promoted by STARC (R&D Dept. & PhD Gr.) and Hirosima-University.

ILDEx (Fuji Research Institute Corporation)
STARC-SPICE (Hitachi ULSI Systems Co.,Ltd.)
PowerSpective and LiCRSIM (Mathematical Systems Inc.)

(1)   TEG Sub Gr. :

TEG-WG leads top-level research and development of design problems on Process Variation, Yield optimization, Data-base-files interfacing between Process/Device and Circuit. Innovative TEG and measurement are the major challenge to achieve the Mission.


(2)   Modeling Sub Gr. (Interconnects):

Timing-closure in VDSM SoC design is the critical and biggest problem. Low Power circuit also be must. Modeling-WG challenges new Circuit-level modeling/simulation on compact MOS model and full LCR power net analysis.


(3)   Modeling Sub Gr. (HiSIM/Benchmark):

Many sophisticated EDA-tools and Models have been extensively proposed, which lead innovative improvement VDSM Physical Design. Benchmark-WG addresses reliable and quick benchmark methodology for these tools and models. Basic idea is special TEG to validate them on Silicon and accurate measurement technique. Open invitation on the TEG, in volunteer base, is continuous policy for annual STARC-TEG designed with updated technologies.