Low Power Technology Group

Semiconductor Technology Academic Reserch Center
Design Technology Development Dept.

• System architecture level
• OS level
• Circuit topology level
• Layout level

Bibliography

System group

Conferences

• "A 9uW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs", K.Ishibashi, T.Yamashita, Y.Arima, I.Minematsu and T.Fujimoto, 2003 IEEE International Solid-State Circuits Conference(ISSCC), Feb.9, 2003 [San Francisco, USA]
• "A 9uW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs", K.Ishibashi, T.Yamashita, Y.Arima, I.Minematsu and T.Fujimoto, Technical report of IEICE, ICD2003-36, May 29, 2003, pp.59-63 [Kanazawa, Japan]
• "A V-driver Circuit for Lowering Power of sub-0.1um Bus", Takahiro Yamashita, Yukio Arima and Koichiro Ishibasi, IEEE 2002 Asia-Pacific conference on ASIC (AP-ASIC 2003), August 8, 2002, pp.267-270 [Taipi, Taiwan]
• "Bus power reduction using V-driver", Takahiro Yamashita, Yukio Arima and Koichiro Ishibasi, Technical report of IEICE, VLD2002-162, ICD2002-227, March 7, 2003, pp.43-47 [Kyoto, Japan]

• NEWS Release on 2/6/2003 (in Japanese)
• MYCOM PC web news headline reported on 4/4/2003

Analog group

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• �hOffset Calibrating Comparator Array for 1.2-V, 6-bit, 4-Gsample/s Flash ADCs using 0.13-um generic CMOS technology", H. Okada, Y. Hashimoto, K. Sakata, T, Tsukada and K. Ishibashi 29th European Solid-State Circuits Conference (ESSCIRC 2003) Sept. 18, 2003 [Estoril, Portugal]
• " An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs", T.Tsukada, Y.Hashimoto, K.Sakata, H.Okada and K.Ishibashi, 2004 IEEE International Solid-State Circuits Conference(ISSCC), Feb.17, 2004 [San Francisco, USA]

  Memory Group

  Under construction...

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