Press Release (Translation of the Japanese original)
| Jan. 22, 2002 | STARC and hd Lab jointly developed "HDL Design Style Guide 2002" |
| July 31, 2000 | STARC and hd Lab jointly developed HDL Design Style Guide |
* Home Page of hd Lab, Inc.
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Jan. 22, 2002
Semiconductor Technology Academic Research Center (STARC)
hd Lab, Inc. |
| STARC and hd Lab jointly developed "HDL Design Style Guide 2002" |
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Semiconductor Technology Academic Research Center (STARC), and hd Lab, Inc. jointly developed "HDL [Hardware Description Language] Design Style Guide 2002."
For the new edition, 78 items have been added to improve design guidance quality.
(1) Items for DFT guidance
(2) Items for low power design
(3) Items for design data management
(4) Improved descriptions
(5) Appendix for using standard synthesis tool
STARC and hdLab will continue joint marketing so that the design style guide will be used widely in design community.
*Publishing schedule and price:
The Design Style Guide 2002 will be published by hd Lab, Verilog-HDL version in 2002/2 and VHDL in 2002/3.
*Design Style Guide:
The Design Style Guide is a guide book with design guidance and design rules.
The first edition "Design Style Guide 2001" had been published in November 2001.
It includes about four hundred rules on basic design restrictions such as naming rules, clock design, hierarchical design, RTL [Register-Transfer Level] description styles and RTL design methods.
The rules are classified into four categories: mandatory, recommended, reference and prohibitions.
In HDL design, some common rules may exist within one group or within one company as an accumulation of their design experiences, but when it comes to the exchange of IP [Intellectual Property] beyond such groups or companies, no common rule exists.
Therefore, even written in the same HDL, it is very difficult to understand the original designer's intention just from HDL codes written outside of the group.
IP distribution is considered to be very important to improve SoC design productivity, but when engineers actually try to re-use IPs developed outside of the design group, they face a lot of trouble.
The Design Style Guide is packed with proven techniques, know-how and design rules that will lead to wide range of IP re-use and successful SoC projects.
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July 31, 2000
Semiconductor Technology Academic Research Center (STARC)
hd Lab, Inc. |
| STARC and hd Lab jointly developed HDL Design Style Guide |
|
Semiconductor Technology Academic Research Center (STARC), and hd Lab, Inc. jointly developed HDL [Hardware Description Language] guide.
The Design Style Guide provides guidance and defines rules for HDL description.
It includes about four hundred rules on basic design restrictions such as naming rules, clock design, hierarchical design, RTL [Register-Transfer Level] description styles and RTL design methods.
The rules are classified into four categories: mandatory, recommended, reference and prohibitions.
STARC and hd Lab have prepared the Design Style Guide for both Verilog and VHDL.
In HDL design, some common rules may exist within one group or within one company as an accumulation of their design experiences, but when it comes to the exchange of IP [Intellectual Property] beyond such groups or companies, no common rule exists.
Therefore, even written in the same HDL, it is very difficult to understand the original designer's intention just from HDL codes written outside of the group.
IP distribution is considered to be very important to improve SoC design productivity, but when engineers actually try to re-use IPs developed outside of the design group, they face a lot of trouble.
The Design Style Guide is packed with proven techniques, know-how and design rules that will lead to wide range of IP re-use and successful SoC projects.
After the publication of the Design Style Guide, STARC will form a working group to gather feedback from users.
The feedback will then be used to make future revisions of the book.
The Design Style Guide will be published by hd Lab this autumn.
It will also be translated in English.
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