STARC-TEG
| STARC-TEG02 |
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* Chip Size
20.5X20.5 mm2
（5X5mm2 16Sub-chipﾟ）
* DRM
90nm ASPLA-DRM
* Contents (Features) -Variability/Yield TEG
-Signal Integrity TEG
-HiSIM‐TEG
-New Interconnects Archi.
-Others SRAM-TEG
IP Process Diagnothis TEG
WLR (Wafer Level Reliability) TEG
* Schedule
2002.08 DRM/Spice
2002.12 Tape Out
2003.04 Wafers（N,U)
2003.06 Report
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| STARC-TEG01 |
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* Chip Size
20X20 mm2
（5X5mm2 16Sub-chipﾟ）
* Features
Process & Device TEG
Variation, Yield etc.
-Signal Integrity TEG (Rev)
-HiSIM RF TEG
-Interconnect DB TEG
ILP/KCR
-Low Pw Gr. TEG
AD,32Bit Adder
-IPReuse TEG
Process Diagnothis TEG (Rev)
-VDEC(Universities）
12Univ. 3 Sub-chip
* Schedule
2001.11 Tape Out（N)
2001.12 Tape Out（U)
2002.03 Wafers（N,U)
2002.04 Report
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