Publication-List from '' Physical Design Group'' @STARC

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English Papers & Publications

(01)	H. Masuda and M. Miura-Mataush "The 100nm MOSFET Model (HiSIM) and its Extension to RF Applications " ISQED Workshop Tutorial, pp. , March. 2002.
(02)	Y. Sasaki, M. Satoh, M. Kumamoto, F. Kikuchi, T. Kawashima, H. Masuda and K. Yano "A crosstalk delay analysis of a o.13um-node Test-chip technology and precise gate-level simulation technology " VLSI Circuit Symposium, pp. , June. 2002.
(03)	A. Kurokawa, T. Sato and H. Masuda "Approximate Formulas Approach for Efficient Inductance Extraction" ASP-DAC, pp. , Jan. 2003. (To be published)
(04)	M. Yamamoto, T. Kohara, H. Masuda "Development of New Large Scale TEG for Evaluation and Analysis of Yield and Variation" ICMTS, pp. , March 2003. (To be published)
(05)	S. Ohkawa, M. Aoki, H. Masuda "Analysis and Characterization of Device Variation in an LSI Chip Using an Integrated Device Matrix Array" ICMTS, pp. , March 2003. (To be published)
(06)	T. Sato, H. Masuda, et al. "Design and measurement of inductance-oscillator for analyzing inductance impact on on-chip interconnect delay" ISQED, pp. , March 2003. (To be published)
(07)	Y. Sasaki, M. Satoh, M. Kumamoto, F. Kikuchi, T. Kawashima, H. Masuda and K. Yano "A crosstalk delay analysis of a o.13um-node Test-chip technology and precise gate-level simulation technology " IEEE SSC, pp. , June. 2003. (To be published)
(08)	A. Kurokawa, K. Hachiya, T. Sato, K. Tokumasu and H. Masuda "Fast on-chip Inductance Extraction of VLSI including angled interconnects" IEICE, pp. , 2003. (To be published)

Japanese Papers & Publications

(01)	H. Masuda: "Physical design in 100nm Technology Era" DA Symposium 2001、pp.95-100, July 2001.
(02)	F. Minami, S. Fujimoto, H.Masuda: "Performance Analysis and Measurement of High Speed On-Chip Transmission-lines" DA Symposium 2001、pp.7-12, July 2001.
(03)	H. Masuda, K. Hara, F. Minami, A. Maruyama, S. Fujimoto: "(Invited) Problems in Physical Design and Activities at STARC" IEICE Technical Workshop, VLD2001-72、pp.25-30, Sept. 2001.
(04)	A.Hashimoto and H. Masuda: "A New Test-Structure to Extract Interconnect-Structure and its Application" 5-th System LSI Workshop, pp.343-346, Nov. 2001.
(05)	H. Masuda: "Physical design in 100nm Technology Era" 5-th System LSI Workshop, pp.103-115, Nov. 2001.
(06)	A.Kurokawa, K.Hachiya, T. Sato, K.Tokumasu and H. Masuda: "A Novel High Speed Extraction Algorithm of VLSI On-chip Inductance including Oblique Interconnects" The 15-th Karuizawa Workshop, pp.487-492, April 2002.
(07)	K.Akutsu, H. Masuda and A.Hashimoto: "Simulation Technology for ILDEx (Interconnects Layer Dielectric Extraction System)" DA Symposium, pp.211-216, July 2002.
(08)	K.Hachiya, A.Kurokawa, T. Sato, F. Minami and H. Masuda: "Extraction of On-Chip Power Net Equivalent Circuit for Dynamic Voltage Bounce Analysis" DA Symposium, pp.193-198, July 2002.
(09)	J.Iwai, K.Machida, Y.Kayama, C.Mizuta, K.Tokumasu and H. Masuda: "New Analysis Tool for Voltage-Bounce Noise on Power-Net Including Power Line Inductance" DA Symposium, pp.205-210, July 2002.
（10）	K.Tokumasu, S.Ito, H. Masuda, H.Ueno, M.Miura-Mataush: "Parameter Extraction of HiSIM Transistor Model" DA Symposium, pp.199-204, July 2002.
（11）	A.Kobayashi and T.Tsuchiya: "Measurement of Power-Net Voltage-Bounce and Verification of Simulation Tool" DA Symposium, pp.241-246, July 2002.
（12）	H. Masuda, H. Hara, F. Minami, A. Maruyama and S. Fujimoto: "(Invited) Physical Design Technologies at STARC: Problems and Activities" IEICE VLSI-Design Technical Workshop, pp.31-36, Aug. 2002.
（13）	H. Masuda: "Trend and Problems on Physical Design Technology in Sub-100nm Era" IEICE Society Workshop, pp. , Sept. 2002.
（14）	F. Minami ,S.Fujimoto and H. Masuda: "Wire Shape Optimization for High Speed Interconnect" IEICE Society Workshop, pp.58, Sept. 2002.
（15）	F. Minami and H. Masuda: "Interconnect Modeling and Shape Optimization for High Speed Design" IEICE VLD-Technical Workshop (Design Gaia), pp.59-64, Nov. 2002.

　　