Publication-List (2002-2003)
from '' Physical Design Group'' @STARC

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English Papers & Publications

H. Masuda and M. Miura-Mataush
"The 100nm MOSFET Model (HiSIM) and its Extension to RF Applications "
ISQED Workshop Tutorial, pp. , March. 2002.
Y. Sasaki, M. Satoh, M. Kumamoto, F. Kikuchi, T. Kawashima, H. Masuda and K. Yano
"A crosstalk delay analysis of a o.13um-node Test-chip technology and precise gate-level simulation technology "
VLSI Circuit Symposium, pp. , June. 2002.
A. Kurokawa, T. Sato and H. Masuda
"Approximate Formulas Approach for Efficient Inductance Extraction"
ASP-DAC, pp.143-148 , Jan. 2003.
M. Yamamoto, T. Kohara, H. Masuda
"Development of New Large Scale TEG for Evaluation and Analysis of Yield and Variation"
ICMTS, pp.53-58 , March 2003.
S. Ohkawa, M. Aoki,  H. Masuda
"Analysis and Characterization of Device Variation in an LSI Chip Using an Integrated Device Matrix Array"
ICMTS, pp.70-75 , March 2003.
A. Kurokawa, K. Hachiya, T. Sato, K. Tokumasu and H. Masuda
"Fast on-chip Inductance Extraction of VLSI including angled interconnects"
IEICE, pp.841-845 , April 2003.
T. Sato, H. Masuda, et al.
"Design and measurement of inductance-oscillator for analyzing inductance impact on on-chip interconnect delay"
ISQED, pp.395-401 , March 2003.
Y. Sasaki, M. Satoh, M. Kumamoto, F. Kikuchi, T. Kawashima, H. Masuda and K. Yano
"A crosstalk delay analysis of a o.13um-node Test-chip technology and precise gate-level simulation technology "
IEEE SSC, pp. , June. 2003.
A. Kurokawa, K. Hachiya, T. Sato, K. Tokumasu and H. Masuda
"Fast on-chip Inductance Extraction of VLSI including angled interconnects"
IEICE, pp.2933-2941 , December 2003.



Japanese Papers & Publications

H. Masuda:
"Physical design 100nm Technology Era"
DA Symposium 2001、pp.95-100, July 2001.
F. Minami, S. Fujimoto, H.Masuda:
"Performance Analysis and Measurement of High Speed On-Chip Transmission-lines"
DA Symposium 2001、pp.7-12, July 2001.
H. Masuda, K. Hara, F. Minami, A. Maruyama, S. Fujimoto:
"(Invited) Problems in Physical Design and Activities at STARC"
IEICE Technical Workshop, VLD2001-72、pp.25-30, Sept. 2001.
A.Hashimoto and H. Masuda:
"A New Test-Structure to Extract Interconnect-Structure and its Application" 
5-th System LSI Workshop, pp.343-346, Nov. 2001.
H. Masuda:
"Physical design in 100nm Technology Era"
5-th System LSI Workshop, pp.103-115, Nov. 2001.
A.Kurokawa, K.Hachiya, T. Sato, K.Tokumasu and H. Masuda:
"A Novel High Speed Extraction Algorithm of VLSI On-chip Inductance including Oblique Interconnects"
The 15-th Karuizawa Workshop, pp.487-492, April 2002.
S.Akutsu, A.Hashimoto and H. Masuda:
"Simulation Technology for ILDEx (Interconnects Layer Dielectric Extraction System)"
DA Symposium, pp.211-216, July 2002.
K.Hachiya, A.Kurokawa, T. Sato, F. Minami and H. Masuda:
"Extraction of On-Chip Power Net Equivalent Circuit for Dynamic Voltage Bounce Analysis"
DA Symposium, pp.193-198, July 2002.
J.Iwai, K.Machida, Y.Kayama, C.Mizuta, K.Tokumasu and H. Masuda:
"New Analysis Tool for Voltage-Bounce Noise on Power-Net Including Power Line Inductance"
DA Symposium, pp.205-210, July 2002.
K.Tokumasu, S.Ito, H. Masuda, H.Ueno, M.Miura-Mataush:
"Parameter Extraction of HiSIM Transistor Model"
DA Symposium, pp.199-204, July 2002.
A.Kobayashi and T.Tsuchiya:
"Measurement of Power-Net Voltage-Bounce and Verification of Simulation Tool"
DA Symposium, pp.241-246, July 2002.
H. Masuda, H. Hara, F. Minami, A. Maruyama and S. Fujimoto:
"(Invited) Physical Design Technologies at STARC: Problems and Activities"
IEICE VLSI-Design Technical Workshop, pp.31-36, Aug. 2002.
H. Masuda:
"Trend and Problems on Physical Design Technology in Sub-100nm Era"
IEICE Society Workshop, pp. , Sept. 2002.
F. Minami ,S.Fujimoto and H. Masuda:
"Wire Shape Optimization for High Speed Interconnect"
IEICE Society Workshop, pp.58-62, Sept. 2002.
F. Minami and H. Masuda:
"Interconnect Modeling and Shape Optimization for High Speed Design"
IEICE VLD-Technical Workshop (Design Gaia), pp.59-64, Nov. 2002.
A. Kurokawa, T. Sato and H. Masuda
"Approximate Formulas Approach for The Efficient Extraction of on-chip mutual-inductance"
IEICE Traus, Fundamentals, pp.2933-2941 , Dec. 2003.
A. Kurokawa, N.Ono, T.Kage, and H. Masuda
"DEPOGIT : Dense power-ground interconnect architecture for physical design integrity"
ASP-DAC, pp., Jan. 2004
C.Mizuta, J.Iwai, K.Machida, T.Kage and H. Masuda:
"Large-scale linear circuit simmulation with an inverse inductance matrix"
ASP-DAC, pp., Jan 2004.
S.Akutsu, N.Ishihara and H. Masuda:
"Anovel test-structure for detail interconnect fabric diagnosis for 90nm process"
ICMTS, pp., March 2004.
M. Yamamoto, Y. Hayashi, H.Endo, and H. Masuda
"Development of a 90nm Large- scale TEG for evaluation and analysis of signal integrity,Yield and variation"
ICMTS, pp. , March 2004.
M. Aoki, S. Okawa, and H. Masuda
"Design guide and process quality improvement for treatment of device variations in an LSI chip"
ICMTS, pp. , March 2004.
K. Nagase, S. Okawa, M. Aoki, and H. Masuda
"Variation status in 100nm CMOS process and below"
ICMTS, pp. , March 2004.
M. Aoki, M. Yamamoto, and H. Masuda
"[Tutorial] Characterization of device variability in LSI chip"
ICMTS, pp. , March 2004.
A. Kurokawa, T. Kanamoto, and T. Sato
"[Tutorial] On-chip inductance? ; Modeling and extraction"
DA Symposium, pp.1-6 , July 2003.
T. Sato, T. Kanamoto, and A. Kurokawa
"[Tutorial] Inductance effects and impacts on VLSI design and signal-integrity"
DA Symposium, pp.7-12 , July 2003.
F. Minami, and H. Masuda
"[Tutorial] Measurement and analysis of interconnects includiny inductive effects"
DA Symposium, pp.13-18 , July 2003.
J. Iwai, K. Machida, C. Mizuta, F. Minami, A. Kurokawa, T. Kage and H. Masuda:
"Development of Power-net Analysis system : PowerSpective"
DA Symposium, pp.49-53, July 2003.
C. Mizuta, T. Kurihara, J. Iwai, K. Machida, T. Kage, and H. Masuda:
"Large Scale Linear circuit simulation with inverse-L technique"
DA Symposium, pp.55-60, July 2003.
Y. Akashi, and F. Minami:
"High trequeney characterization of LSI interconnects"
DA Symposium, pp.61-66, July 2003.
S. Ono, A. Kurokawa, T. Kage and H. Masuda:
"Interconnect architecture for Physical design integrity"
DA Symposium, pp.67-72, July 2003.
K. Morikawa, A. Kobayashi, S. Ito, H. Masuda, M. Goto, and Y. Kondo:
"Transistor-and Circuit-level Auto benchimark technology for Compact MOSFET models"
DA Symposium, pp.237-240, July 2003.
S. Ito, K. Morikawa, A. Kobayashi, H. Masuda, S. Fujimoto, T. MIzoguchi, H. Ueno, and M. Miura:
"Parameter extraction of HiSIM 1.1 / HiSIM 1.2"
DA Symposium, pp.247-252, July 2003.
A. Kurokawa, S. Ono, T. Kage, Y. Inoue, and H. Masuda:
"New interconnect architecture for Physical design integrity"
IEICE Technical Workshop, pp., Dec 2003.




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