| STARC-TEG |
| STARC-TEG02 |
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* Chip Size
20.5X20.5 mm2
i5X5mm2 16Sub-chipίj
* DRM
90nm ASPLA-DRM
* Contents (Features) -Variability/Yield TEG
-Signal Integrity TEG
-HiSIM]TEG
-New Interconnects Archi.
-Others SRAM-TEG
IP Process Diagnothis TEG
WLR (Wafer Level Reliability) TEG
* Schedule
2002.08 DRM/Spice
2002.12 Tape Out
2003.04 WafersiN,U)
2003.06 Report
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| STARC-TEG01 |
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* Chip Size
20X20 mm2
i5X5mm2 16Sub-chipίj
* Features
Process & Device TEG
Variation, Yield etc.
-Signal Integrity TEG (Rev)
-HiSIM RF TEG
-Interconnect DB TEG
ILP/KCR
-Low Pw Gr. TEG
AD,32Bit Adder
-IPReuse TEG
Process Diagnothis TEG (Rev)
-VDEC(Universitiesj
12Univ. 3 Sub-chip
* Schedule
2001.11 Tape OutiN)
2001.12 Tape OutiU)
2002.03 WafersiN,U)
2002.04 Report
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| STARC-TEG00 |
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* Signal Integrity Characterization @@
TEG (Group of Test-Structures) |High Freq. Clock Lines
|Crosstalk
|Vcc/Vss Voltage Bounce
|Substrate Transmission Noise
|High Freq. Analog MOS
|Interconnect Capacitance DB
|Loaded Ring-Oscillator
|Standard Cell Library
|Process Variation Characterize
>500 Test StructuresAMax 200KG Integrity
* Focus on Freq. Characterization
(DC]20GHz)
* Schedule 2000.10 Tape Out
2001.02 WafersiN,T)
2001.05 Report
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