Mr. T.Sato from Hitachi (now,Renesus Technology) and Dr.H.Masuda from STARC
received
"BEST PAPER AWARD" at International on Quality Electronic Design
(ISQED), held at Monterey CA in March 2003.
The title of the paper is:
"Design and measurement of inductance-oscillator for analyzing inductance
impact on on-chip interconnect delay"
This work has been conducted as a part of activities in the "Interconnect
Sub-Working Group
(SWG)" of STARC since 2001. Many young and talented Engineers join
the SWG, from STARC Sponsor-Industries and EDA Companies in Japan, who
dominate the research and development works together.
The other key activity at STARC is the Full-Chip Test structure (TEG) and Wafer fabrication
with updated process technology.
Both closely together to generate such a excellent work on Physical Design
issue, including on-chip inductance analysis and Signal Integrity design.
Physical Design Group of STARC hopes many people join the STARC-promoted
SWG to work together towards practical solutions on upcoming VDSM Physical
Design problems.
Hiroo Masuda
STARC, Physical Design Group, Group-Leader
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