Technical Program
| SUNDAY, APRIL 8 |
| 7:00 - 9:00 pm | Registration and Reception |
| MONDAY, APRIL 9 |
| 8:00 - 8:30 am | CONTINENTAL BREAKFAST |
| 8:30 - 8:45 am | WELCOME
David Hathaway (IBM Microelectronics), General Chair
Andrew B. Kahng (UCSD), Program Chair |
| 8:45 - 9:30 am | KEYNOTE 1
General Issues in ASIC Design: Business and Methodology, George Doerre (IBM Microelectronics) |
| 9:30 - 9:45 am | Break |
| 9:45 -11:45 am | SESSION 1: DESIGN METHODOLOGY CAPTURE AND MANAGEMENT
0945-1015 "Status and Evolution of IP Symphony", David Dick (Fujitsu)
1015-1045 "Fast Integration of EDA Tools and Scripting Language", Pinhong Chen (UC Berkeley / TSMC North America) and Kurt Keutzer (UC Berkeley)
1045-1115 "The UEDK: A VLSI CAD/EDA Learning-by-Example Platform", Jose' A.D.F. Lima (U. do Minho, Portugal)
1115-1145 Moderated Discussion, Workshop Attendees |
| 11:45 -12:45 pm | Lunch |
| 12:45 - 2:45 pm | SESSION 2: TOOL AND METHODOLOGY MEASUREMENT
1245-1315 "Key Performance Indicators of Methodology Capability", Ron Collett (Numetrics)
1315-1345 "Optimizing Cycle Time Through the Use of Design Metrics", Bill Bell (TI)
1345-1430 PANEL: Design and CAD Metrics
- "On High Level Estimators and Constructors", Majid Sarrafzadeh and Jason Cong (UCLA)
- "A METRICS System for Design Process Optimization", Andrew B. Kahng (UCSD) and Stefanus Mantik (UCLA / Cadence)
- "Tool Benchmarking: Status and Directions", Justin Harlow (SRC)
1430-1445 Moderated Discussion, Workshop Attendees |
| 2:45 - 3:00 pm | Break |
| 3:00 - 5:30 pm | SESSION 3: FRONT-END PLANNING AND PD METHODOLOGY
1500-1530 "A Eulogy for Wireload Models", Bill Bell (TI)
1530-1600 "Datamodels for Physical Synthesis: Some Practical Considerations for Library Support", Dwight Hill and Shir-Shen Chang (Synopsys)
1600-1630 "Design Planning Methodology for Rapid Chip Deployment", David E. Lackey (IBM Microelectronics)
1630-1700 "Open Design Rule Markup Language for STARC Open Design Rule Initiative", Takahide Inoue (UC Berkeley and JSIG VSIA), Hiroyuki Hara (STARC) and Tadahiko Nakamura (STARC) (
paper)
1700-1730 Moderated Discussion, Workshop Attendees |
| 6:00 - 9:00 pm | DINNER
Presentation and Discussion, Workshop Attendees
"Design Processes Roadmap in the 2001 ITRS: Current Draft and Open Issues", Don Cottrell (SI2 and member, U.S. Design TWG for ITRS-2001) |
| TUESDAY, APRIL 10 |
| 7:30 - 8:15 am | CONTINENTAL BREAKFAST |
| 8:15 - 9:45 am | SESSION 4: LIQUID LIBRARY AND PERFORMANCE OPTIMIZATION METHODOLOGIES
0815-0845 "Semicustom Design: Synergies Between Full Custom and ASIC Design Flows in High-Performance Processor Design", Greg Northrop (IBM Research)
0845-0915 "Power and Performance Optimization of Cell-Based Designs with Intelligent Transistor Sizing and Cell Creation", Etsuji Yoneno (Hitachi ULSI Systems) and Philippe Hurat (NTI/Cadabra)
0915-0945 Moderated Discussion, Workshop Attendees |
| 9:45 - 10:00 am | Break |
| 10:00 -12:00 pm | SESSION 5: NANOMETER AND RTL-DOWN CLOSURE
1000-1030 "RTL-Down Data Models and Convergence Methodology", Patrick Groeneveld (Magma)
1030-1100 "Data Modeling and Convergence Methodology in Integration Ensemble", Lou Scheffer (Cadence)
1100-1145 PANEL: Physical Design Methodology Best Practices
- Salil Raje (Monterey)
- Paul Rodman (Reshape)
- Aurangzeb Khan (Simplex/Altius)
1145-1200 Moderated Discussion, Workshop Attendees |
| 12:00 - 1:30 pm | LUNCH AND KEYNOTE 2
"The IC Implementation Tool Set", Gary Smith (Dataquest) |
| 1:30 - 3:30 pm | SESSION 6: MODELING AND METHODOLOGY FOR SOC AND SYSTEM DESIGN
1330-1400 "SOC Verification Software - Test Operating System", Robert Devins (IBM Microelectronics)
1400-1430 "High-Level Design Modeling and Design Handoff", Rajesh Gupta (UC Irvine)
1430-1500 "Using Esterel Approach to Design Complex Systems", Gilles Pelissier (STMicroelectronics) and Lionel Blanc (Esterel Technologies)
1500-1530 Moderated Discussion, Workshop Attendees |
| 3:30 - 3:45 pm | Break |
| 3:45 - 5:45 pm | SESSION 7: ANALOG AND ANALOG-MIXED-SIGNAL (A/AMS) DESIGN FLOWS
1545-1610 "A Formal Top-Down Design Process of Analog Mixed-Signal Circuits", Ken Kundert (Cadence)
1610-1635 "Changing Paradigms - Fast-Turn Mixed Signal RF IP", James Spoto (Enablix Solutions)
1635-1700 "Current Analog Design Methodologies and Practices", Bull Guthrie (Numetrics)
1700-1725 "Trends in AMS Design Methodology, Gary Smith (Dataquest)
1725-1745 Moderated Discussion, Workshop Attendees |
| 5:45 pm | Adjourn |
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