| MONDAY, July 23 |
| 15:00-16:40 | SESSION A-2: Deep Sub-Micron Design |
| 15:00-15:25 |
(2) "Experiments and Analysis of Transmission Line Characteristic in High Speed LSIs", Fumihiro Minami, Shinichi Fujimoto and Hiroo Masuda (STARC) |
| TUESDAY, July 24 |
| 9:00-10:40 | SESSION A-4: STARC's Special Session "Challenge to SoC Design Technology" |
| 9:00- 9:25 |
(14) "Towards the Revolution of SoC Design Technology", Kenji Yoshida (STARC) |
| 9:25- 9:50 |
(15) "IP Reuse and Delivery for SoC Design Demand Silicon Proven IPs", Tadahiko Nakamura and Masanori Imai (STARC) |
| 9:50-10:15 |
(16) "System Level Design Methodology of Next Generation SoC", Michiaki Muraoka (STARC) |
| 10:15-10:40 |
(17) "Physical Design in 100nm Technology Era", Hiroo Masuda (STARC) |
| WEDNESDAY, July 25 |
| 10:50-12:05 | SESSION B-10: Analysis Model |
| 10:50-11:15 |
(41) "Design Rule Markup Language for STARC Open Design Rule Initiative", Hiroyuki Hara (STARC), Takahide Inoue (University of California at Berkeley/ VSIA JSIG) and Tadahiko Nakamura (STARC) |