IP Modeling
For IP verification

Overview

It's been increasingly apparent that IP quality, especially functional quality of IP, is essential for IP reuse promotion. We need exhaustive IP functional verifications here. On the other hand, functional verification phases consume from 50 to 80 percent of a total SoC development time. Productivity improvements in the IP verification process is required strongly. There is a trade-off here. IP Reuse group addresses these problems relevant to the IP modeling for functional verifications to mitigate this trade-off. In addition to this activity, we start to tackle the IP modeling relevant to the implementation such as the timing model for IP, collaborating with Design Methodology group(it leads).

Activities

　An modeling guideline of External Functional Model for leveraging their reuse in test benches is required due to diversified IP functional verification environments within both companies and their departments. Here External Functional Model, we call, is the model that drives a test scenario and changes the inputs of DUT at signal level or higher level.

①Modeling guideline for IP External Functional Verification Model Its second version is under being developed based on the preliminary version developed in 2003.
②Guideline for assertion description We performed the comparison among several assertion description languages in 2003. Using this result, we are going to develop the guideline for assertion description contributing to extensive reuse in the second half of this year.
We show the relation among IP external functional verification model, test bench and assertion monitor below.